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Altera_Forum's avatar
Altera_Forum
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18 years ago

Stratix II PLL will not lock!?

I have a design where the (fast) pll (#1) that controls the primary clock on the device will not lock to the reference clock.

The problem I have is that if I remove all the logic from the design and only keep the pll chain pll# 1 locks. The confusing part is the pll chain in question has no connections to the rest of the design when everything is implemented. So I am finding it hard to find the problem that is causing the PLL not to lock.

Anyone have any suggestions on how I can find out why this pll is not locking, or suggest any app notes or reference manuals that may help?

Thanks

Rob :confused:

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Unrelated logic might affect how much noise the PLL is exposed to. Could there be a missing or bad PLL power/ground connection that becomes a problem only when the toggling logic creates some noise in the device?

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    The PLL's require quite clean supplies. What IO standard are you using for your regular IO? If you have left it as default, its probably 3.3v LVTTL which is about 20mA as standard which is too high in my opinion. If you have loads of IO all changing state at the same time you could get SSN (Simultaneous Switching Noise) which causes noise on the supplies and GND.

    If you are using 3.3v LVTTL, I would recommend trying LVCMOS 3.3v and set the current strength to 4mA instead which is more than enough for point to point signalling. I doubt you would ever need more than 8mA when using 3.3v LVCMOS.

    What is your PSU decoupling like? you could measure the PLL locked OP of the pll with a scope, and simultaneously measure the PLL supply. trigger off the PLL OP and if the two edges tie up, then bingo, you know your PSU is too noisy.

    Hope this gives you something to think about.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    if the clock at the input pin of the fpga for the pll clock input is drifting, the lock

    will go down.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I would recommend that you first verify that all the PLL supply (VCC) and GND are properly wired and getting power as per device recommendations. Then check for the input clock to the PLL, whether the clock is clean, non-drifting and with proper IO standard. Also, verify the PLL control signals (if they are used, e.g., areset, pllen, etc.) are in correct order.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Thank you everyone for your responses, however BD_SLS got it right, the ferrit bead that filters the power to the pll was not assemblied properly. I found out late yesterday that it was not solder to pad that runs to the power pin of the pll.

    Thanks again for all your advance.

    Rob:)