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Altera_Forum
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19 years ago

Stratix II PLL will not lock!?

I have a design where the (fast) pll (#1) that controls the primary clock on the device will not lock to the reference clock. The problem I have is that if I remove all the logic from the desi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Thank you everyone for your responses, however BD_SLS got it right, the ferrit bead that filters the power to the pll was not assemblied properly. I found out late yesterday that it was not solder to pad that runs to the power pin of the pll.

Thanks again for all your advance.

Rob:)