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Altera_Forum
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18 years ago

Stratix II PLL will not lock!?

I have a design where the (fast) pll (#1) that controls the primary clock on the device will not lock to the reference clock. The problem I have is that if I remove all the logic from the desi...
Altera_Forum's avatar
Altera_Forum
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18 years ago

if the clock at the input pin of the fpga for the pll clock input is drifting, the lock

will go down.