Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorStratix II PLL will not lock!?
I have a design where the (fast) pll (#1) that controls the primary clock on the device will not lock to the reference clock. The problem I have is that if I remove all the logic from the desi...
Altera_ForumHonored Contributor
Honored Contributorif the clock at the input pin of the fpga for the pll clock input is drifting, the lock
will go down.
