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Altera_Forum
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18 years ago

Stratix II PLL will not lock!?

I have a design where the (fast) pll (#1) that controls the primary clock on the device will not lock to the reference clock. The problem I have is that if I remove all the logic from the desi...
Altera_Forum's avatar
Altera_Forum
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18 years ago

I would recommend that you first verify that all the PLL supply (VCC) and GND are properly wired and getting power as per device recommendations. Then check for the input clock to the PLL, whether the clock is clean, non-drifting and with proper IO standard. Also, verify the PLL control signals (if they are used, e.g., areset, pllen, etc.) are in correct order.