Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorStratix II PLL will not lock!?
I have a design where the (fast) pll (#1) that controls the primary clock on the device will not lock to the reference clock. The problem I have is that if I remove all the logic from the desi...
Altera_ForumHonored Contributor
Honored ContributorUnrelated logic might affect how much noise the PLL is exposed to. Could there be a missing or bad PLL power/ground connection that becomes a problem only when the toggling logic creates some noise in the device?
