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Honored Contributor

18 years ago

Stratix II PLL will not lock!?

I have a design where the (fast) pll (#1) that controls the primary clock on the device will not lock to the reference clock. The problem I have is that if I remove all the logic from the desi...

Altera_Forum

Honored Contributor

18 years ago

Unrelated logic might affect how much noise the PLL is exposed to. Could there be a missing or bad PLL power/ground connection that becomes a problem only when the toggling logic creates some noise in the device?

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Stratix II PLL will not lock!?

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