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OrF's avatar
OrF
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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Stratix 10M DIB Module

Hi

I'm using the DIB to inter connect between the 2 dies of the Stratix 10

I'm using it in BYPASS (therefore I need to define the constraints) mode and one of the IO is transferring clock from one side to another - source synchronous.

I generated DIB Module from the IP catalog (dib_rx_altera_dib_1930_u7lqq6i)

at the synthesis / fitter stage I would like to assign the constraints to the IO

the question is to where should I assign / define the Clock in the constraints , and the input delay ?

to DIE1_dib_pad_2_22_2[18] or to OUT[18] (in the case of the Clock) , and similar to the input delay ?

if I will assign Input Side DIE1_dib_pad_2_22_2[18] - will quartos/ timing analyzer will understand that OUT[18] is a clock (and take into account the routing delay) ?

or the dib_0 module is Blackbox for the timing analyzer and I should define the clock and IO input delays on the OUT[18] ?

my understanding that the input from the EMIB inserted to the Die1 via DIE1_dib_pad_2_22_2[18] , dib_0 module does nothing in bypass mode (just routing) , and the OUT[18] is the continuation of the wire .

thanks

Or.

  • Nurina's avatar
    Nurina
    3 years ago

    Hi,


    I cannot seem to get engineering to confirm the values, but the normal practice is by adjustment.

    You can start with the values they put for the example design and fine tune it after compilation.

    Below are the values used:

    • max C=2.65
    • min C=-2.65
    • max A + max B = 8.25
    • min A + min B = 3
    • max D + max E = 4.75
    • min D + min E = -1.64


    Regards,

    Nurina


20 Replies

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  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Or,


    1. The clock should be virtual clocks, so there shouldn't be a target. You just need to define the period and name of the clock and Timing Analyzer will create a virtual clock.
    2. What do you mean by system synchronous, how is it different from your source synchronous design?
    3. The B,C,D timing values from Figure 16 of the above document is as follows. B=D=DIB Latency=2.5ns as mentioned here https://www.intel.com/content/www/us/en/docs/programmable/683142/20-2-19-3-0/latency.html. EMIB Delay=C=Wire Delay of Stratix 10
    4. The set_input/output_delay should be targeting the virtual clocks and the ports connected to DIE1_dib_pad_2_22*
    5. <<my understanding that the input from the EMIB inserted to the Die1 via DIE1_dib_pad_2_22_2[18] , dib_0 module does nothing in bypass mode (just routing) , and the OUT[18] is the continuation of the wire .>> Is this specific to your design? If not, then you may apply the timing constraints as suggested above.


    There is a DIB IP example design, you can generate this in the Platform Designer. You may refer to this example design for the timing constraints.


    Regards,

    Nurina


    • OrF's avatar
      OrF
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      Hi Nurina

      1. Clock should be assign to IO – when constraining Source Synchronous interfaces

      Look at this training and document and trainings from Intel/Altera.

      https://learning.intel.com/Developer/learn/course/168/play/1632:223/constraining-source-synchronous-interfaces

      Slide 12,27

      https://cdrdv2-public.intel.com/653688/an433.pdf

      Section Output Clock Constraints and Input Clock Constraints

      1. in System Synchronous – the clock is not transferred with the Data (as in Source Synchronous) – in system Synchronous the clock is transferred to both devices , and should be aligned.
      2. where can I find “EMIB Delay=C=Wire Delay of Stratix 10” Values , I search and find nothing about it . which document describes it ?

      Searching for EMIB in this document finds nothing.

      1. This is not accurate according to “Source Synchronous interface “ - see course and document above .

      The output delays of the “Transmitting Device “ is assign to the clock which defined on the output Pin . / Slide 26 ,31 at the training

      For the Receiving Device ,you are right, the input delay is according the virtual clock .

      1. This is not specific from my implementation this is Module I get when I generated the DIB module .
  • OrF's avatar
    OrF
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi

    1SG10MHN3F74C2LG_U1,
    1SG10MHN3F74C2LG_U2,

    Thanks

    Or.

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Or,


    Apologies for the late reply.

    May I know which device you are targeting? Can you provide the OPN?


    Thanks,

    Nurina


    • OrF's avatar
      OrF
      Icon for Occasional Contributor rankOccasional Contributor
      3 years ago

      I'm aware of this document ,

      The document leaves many open questions , and does not refer to my questions.

      1. The document is talking about system synchronous and not Source synchronous as my case.
      2. I didn't find any place that specifies the values of B,C,D Timing values (at the Figure 16) the only timing which was specifies is 2.5ns, it is not written if 2.5ns = EMIB Delay (C values) , or the DIB Latency (B,D values) - or all the values together .
      3. My question was to where should I set the input/output delays practically in the SDC, which means to which pins or ports?, it is not written in the document , what is the dib_0 module (in my original question) stand for , is it the "Die B DIB" (at figure 16)? or it is " EMIB+DIE B DIB " ?
      4. The importance of item 3 above is to understand if quartos timing analyzer , takes into account the internal routing of dib_0 and derived the clock definition in the input side and add the Routing delay inside the dib_0 module

      Thanks

      Or