Occasional ContributorHi,
I would be using an I2C IP on the Stratix10 FPGA.
What is the maximum speed of operation of this I2C IP.
Is it interns of Giga or Megha Hertz would like to know the exact frequency range the I2C IP can work.
Thanks
Regular ContributorHi kiransr,
May I know which IP which you are referring to according to the embedded peripheral IP user guide?
https://www.intel.com/content/www/us/en/docs/programmable/683130/24-1/introduction.html
Thanks.
Regards,
Aik Eu
Occasional ContributorHi Aik Eu,
The IP which I was referring to was
I2c Slave to Avalon-MM Master Bridge Intl FPGA IP
And the I2C IP which is used along with ARM hard processor.
For both of these IP would like to know the speed of operation.
Regards,
Kiran
Occasional ContributorHi Aik Eu,
The IP that I was referring to was LVDS Serdes IP, available in the library basic functions IO section.
And also, I would like to know about the mini LVDS IO how long it can drive.
Both of my questions are related to LVDS.
Regards,
Kiran
Occasional ContributorHi Aik Eu,
Actually, you mentioned standard I2C max clock frequency of 100khz is it correct.
We are using the Intel stratix10 soc FPGA in that we will be using the I2C IP in the ultra-fast mode of operation so, will it be working at a speed of 1Gigahertz.
Regards,
Kiran
Super ContributorHi, you are above referring to I2C interface of Stratix 10 Hard Processor. It's maximal speed is specified in Technical Reference Manual with 400 Kbps.
Generally, what's the idea behind bridging HPS I2C to AVMM master in your design? According to user guide, Intel FPGA I2C Agent to Avalon-MM Host Bridge Core is specifically intended to drive flash memory. Also this core is limited to 400 Kbps speed.
Gbps speed is simply impossible by nature of the I2C interface as open drain bus with asynchronous clock and arbitration
Occasional ContributorHi FvM,
Thank you.
It's not in gigahertz, my question should be will the I2C be working at some meghahertz speed, if so what's that speed.
Regards,
Kiran
Super ContributorHi,
no, 400 Kbps (400 kHz) maximal, as specified. Special fast I2C variant can achieve higher speed by using push-pull drivers, obviously the discussed IP doesn't provide it.
Still not clear what you want to achieve.
Regards,
Frank
Occasional ContributorHi Frank,
Thank you for the reply.
You mentioned about the special fast I2C variant, where/how can I get access to this special fast I2C variant and will it run at a speed of 1Mhz.
And if that special fast I2C is used in Stratic10 soc FPGA, will the open drain IO pads support speed of 1Mhz.
Are there Open-Drain pads in Stratix 10 device that can run at 1Mhz.
Can you provide detailed explanation on this.
Regards,
Kiran
Regular ContributorHi
Sorry to mention that the Stratix10 only supports up to Fast Mode of the I2c protocol.
For the Stratix10 I2C controller maximum speed is up to 400Khz.
This is mentioned in the Stratix10 TRM :
https://www.intel.com/programmable/technical-pdfs/683222.pdf
It is the same if you are using the I2C Host IP :
https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/core-overview-35558.html
Regards
Jingyang, Teh
Occasional ContributorHi Jingyang Teh,
Thank you for the answer.
If we port ASIC verified I2C (our own I2C module, which can run at 1.3Mhz) to stratix 10 FPGA then will the IO's support the same speed as ASIC (1.3Mhz) or will it be restricted to 400Khz.
Regards,
Kiran
Occasional ContributorHi Jingyang,
Please let me know -
Are there Open-Drain IO pads in Stratix 10 device that can run at 1Mhz or above?
Thanks,
Kiran
Super ContributorHi,
documentation clearly specifies to support 400 kHz maximal. To find out what's the actual limitation, you probably need to get familiar with the documentation and IP core details yourself.
In case of soft I2C IP, speed is fixed to 100 and 400 kHz, there's one bit to switch between both. Using a different speed would require to modify the IP source code.
Stratix 10 HPS has preset SCL high and low clock tic counts for standard and fast mode. I read the documentation so, that lower counts are possible (see 20.4.5.1. Minimum High and Low Counts). If I2C can actually operate with lower settings must be tested.
I2C operation speed is not only limited by controller timing but also by time constant (pull-up resistor and load capacitance) of open drain bus. Intel I2C IP doesn't support push-pull bus drivers for Hs mode.
Occasional ContributorHi,
Please understand my query,
I am not asking for I2C soft IP speed and its limitations. My query is not around I2C, my question is all about
open-drain IOs that come with stratix-10 device.
Please let me know - what is the max speed the open-drain IO can operate ?
Thanks,
Kiran
Occasional Contributorso, do you mean - that Stratix-10 open-drain IO is limited to operate upto max 400KHz, time-constant of open-drain IO does not support to run beyond 400Khz ? Please request for a binary answer.
Regular ContributorHi
Yes the Stratix10 Single Ended IO could support up to 100Mhz.
Running 1Mhz should be not a problem.
Regards
Jingyang, Teh
Regular ContributorHi
Do you have any follow up question on this case?
Regards
Jingyang, Teh
Occasional ContributorHi Jingyang,
Have no further questions, you can close this.
Regards,
Kiran
