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Honored ContributorSRAM interface timing discrepancy from Quartus-II 7.0 and 9.0
I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484C7. Recently, I updated the design software to Quartus-II 9.0 SP1, the same design was compiled successfully. However, the design didn't work on my target board. The NIOS-II didn't start. The debugger stopped before my application code. It took a while for me to find what causes the problem. I found that it was caused by SRAM interface timing from Quartus-II 9.0 SP1. When I reduce the PLL phase shift to -4.5ns, it starts to work while in Quartus-II 7.0, it can work when the PLL phase shift is set upto -6.7ns. Although this problem has been resolved, I want to know if there are other discrepancies or any implications. Many thanks.
13 Replies
Altera_Forumeven with SRAM, if your phase shift might be a problem then heat the target up and also cool it down. if your target has temperatur problems then you should recheck for setup and hold time. if your design is cooled down, the fpga gets faster and the hold time becomes more critical. also check your quartus settings fast input out registers and other stuff.
- Altera_Forum
Kaz,
Thank you very much indeed for your looking into my problem. It is SRAM not SDRAM. The compiled design by Quartus-II 7.0 worked on the same target board at almost the same time as the design by Quartus-II 9.0SP1. I would say that any difference of physical conditions can be ruled out. Best regards, BC - Altera_Forum
looks like you haven't optimised the sdram IF timing window, so it is edgy. try heating up your board with a hair dryer or cool it down with freezing spray and see what happens.
