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Altera_Forum
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16 years ago

SRAM interface timing discrepancy from Quartus-II 7.0 and 9.0

I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

even with SRAM, if your phase shift might be a problem then heat the target up and also cool it down. if your target has temperatur problems then you should recheck for setup and hold time. if your design is cooled down, the fpga gets faster and the hold time becomes more critical. also check your quartus settings fast input out registers and other stuff.