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Altera_Forum
Honored Contributor
Honored ContributorSRAM interface timing discrepancy from Quartus-II 7.0 and 9.0
I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484...
Altera_ForumHonored Contributor
Honored Contributorlooks like you haven't optimised the sdram IF timing window, so it is edgy. try heating up your board with a hair dryer or cool it down with freezing spray and see what happens.
