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Altera_Forum
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17 years ago

SRAM interface timing discrepancy from Quartus-II 7.0 and 9.0

I have a design which contains an SRAM interface with the default PLL phase shift, -4.8ns for this SRAM. It was compiled by Quartus-II 7.0 and it works perfectly on my target board with an EP2C20F484...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Kaz,

Thank you very much indeed for your looking into my problem.

It is SRAM not SDRAM. The compiled design by Quartus-II 7.0 worked on the same target board at almost the same time as the design by Quartus-II 9.0SP1. I would say that any difference of physical conditions can be ruled out.

Best regards,

BC