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Altera_Forum
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13 years ago

SPI with DMA is not working?

Hi, everyone

I am using SPI Master Core on FPGA to transmit data to SPI slave (offboard device). I want to use DMA to free my NIOS for other tasks during SPI data transfer. My Idea is

NIOS - DMA - SPI(master) <-> SPI (slave / extern device)

I can not understand, how can it work.

SPI master core send and receive data at the same time. After sending, e.g, 8 bits data I also have to read the 8 bits data in RXdata register which resets RRDY bit in status register. Otherwise I will get a ROE (Receive overrun error), If I send another 8 bits data.

If I use DMA to send, e.g., 20 bytes data continiously without reading any data from SPI Rxdata, I will definetely get error and Sending will not be successful.

Has someboby really used SPI with DMA to send data? How can it work?

Thanks a lot!

20 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Why not to use SPI to Avalon-ST and SGDMA? SGDMA would transfer the data, when SPI core is ready.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks U a lot dear Socrates

    Do U have an Example ? QSys & Source Code.

    If I use SGDMA, I will need a SGDMA memory to steam for TX.

    Do I also need a SGDMA stream to memory for RX to avoid RX overrun error? I do not need to receive data.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I've not used SPI with Avalon-ST interface, but since it's a streaming interface, there should be no problems if You will not use data reception part, since it's not keeping data in any buffer. Check documentation.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks again Socrates!

    I don't think it is a problem with DMA or SGDMA, but with SPI. I must receive RXdata everytime I have sent TXdata. Or I would get Receiver Overrun Error.

    I don't want to interrupt Txdata channel after each sending in order to receive unused Rxdata and so to reset RRDY bit in status register.

    has somebody Idea?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    SPI with Avalon-ST is a different component than simple SPI, which has Avalon-MM interface, so there are no interrupts, no overrun errors and that kind of stuff! Either You don't understand what I am talking about or this task is too difficult for You.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi thanks, this post makes sence. PS.: I am a beginner of Altera FPGA and may ask lots of stupid questions.:)

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    But sorry, The avalon Streaming (Avalon-ST) SPI core is an SPI slave. And my offboard SPI Interface is also Slave.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Writing an MM-Slave wrapper around a general SPI-master is not that difficult.

    What specific device is your external SPI slave?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Writing an MM-Slave wrapper around a general SPI-master is not that difficult.

    What specific device is your external SPI slave?

    --- Quote End ---

    It is a MPU serial Interface consisting of serial clock SCLK, serial data SDIN, D/C (data/command), and ChipSelect. this SPI is used to receive display command and data. To control D/C I generated a PIO. To serial data SDIN is MOSI of SPI in FPGA. And MISO of SPI in FPGA is not used.

    What do U mean "Writing an MM-Slave wrapper around a general SPI-master is not that difficult."

    I tested sending data to SPI with DMA. But without reseting RXdata I can only send Txdata twice due to, I think, receive overrun error.

    My Idea is to shut off Rxdata path and its Error bit of status register in SPI master on FPGA. Is it possible?

    Thanks all of U guys and have a good day.