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Altera_Forum
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13 years ago --- Quote Start --- Avalon MM master : waitrequest Avalon MM slave: dataavailable, endofpacket & readyfordata How can it work? Thanks --- Quote End --- It doesn't. The MM interface hasn't got a waitrequest to hold the DMA off, effectively resulting in a TXOverrun at the second write. The dataavailable and readyfordata are internally connected only and read as 'status' signals by a Nios II CPU. Maybe you can try inverting the readyfordata and use that as a waitrequest.