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It doesn't. The MM interface hasn't got a waitrequest to hold the DMA off, effectively resulting in a TXOverrun at the second write.
The dataavailable and readyfordata are internally connected only and read as 'status' signals by a Nios II CPU.
Maybe you can try inverting the readyfordata and use that as a waitrequest.
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In V file I found
// Ready to accept streaming data.
assign readyfordata = TRDY;
the signal readyfordata indicates if Transmit ready bit is set. Inverting the readyfordata/TRDY for every write prevents my NIOS from doing other tasks. Or do U mean I should change hardware to do it? thanks
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