Sopc Help

Yes, i have 2 images to be stored at the same time.

(2 camera's -> 1 memory).

The arbiter integer are standard 1 (as in the picture).

And i enabled a burst of 32 while the template FIFO is 256.

Is a burst of 32 enough ?

And what does a burst of 32 means? That the master has 32 clk cycles acces to the slave or that 32 data transfer occur to the slave?

Like u said, the slave needs some cycle to set the adress.

I think you should use some signaltap probes to see what is happening and why your masters are frozen for so long.

One possible explanation could be that you have two masters trying to access different portions of memory at the same time, and the arbitrator is letting each one access one word at a time. In that case you loose all the latency cycles from the DRAM on each access.

The master interface has some features to speed up the access, such as bursts and/or pipelined transfers with arbitrator lock. You should look into those, to let your masters access several words in a row and avoid most of the lost latency cycles.

I'll test that.

But I also have a question: Some of my write masters get a buffer full. Fifo dept is 258 and there should be enough of time to write them to the SDRAM. If i assing a GO to 2 components at the same time the arbiter can handle that ... right or not?

where are your failing paths? Adding the pipelines should already help, but in some cases it can be the design inside your component that can be the problem.

Do you have the same problem with less masters in your SOPC design?