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Altera_Forum
Honored Contributor
Honored ContributorSopc Help
hi again, I'm using a SDRAM controller in SOPC. but things are not working right. Failing paths, buffer of templates are getting full , ... I'm using master write and master read ...
Altera_ForumHonored Contributor
Honored ContributorYes, i have 2 images to be stored at the same time.
(2 camera's -> 1 memory). The arbiter integer are standard 1 (as in the picture). And i enabled a burst of 32 while the template FIFO is 256. Is a burst of 32 enough ? And what does a burst of 32 means? That the master has 32 clk cycles acces to the slave or that 32 data transfer occur to the slave? Like u said, the slave needs some cycle to set the adress.
