Honored ContributorHi all,
I generated 8 Master templates (read and write together) and one slave sdram component. When i compile the device gives the warning timing requirements not met. In the timingsadvisor i made alle the recommende settings except : - Duplicate logic for fan-out control - Use location asignments & back-annotation - Use fast input, fast output, and fast output enable registers What else can i do, to fit timing?
Honored ContributorI would put some pipeline bridges into those paths. Perhaps connect four of the masters to on bridge, the other four master to another bridge, then connect those two bridges to the SDRAM controller. If that's not enough then perhaps change the bridge topology slightly. Here is a document that talks about this in more detail: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf
Honored ContributorThx,
Reading it*Honored ContributorIf u have several masters, is there an arbiter added by the sopc builder? Or do you have to add one? And i'll try to add pipelined bridges, thx!
Honored ContributorThe arbiters are automatically added by SOPC builder, when several masters are connected to the same slave.
Honored ContributorThen i have another question. as said above i use 8 Master Templates thas uses 1 Slave SDRAM controller.
If all templates do an action read or write at the same time... Will the arbiter handle every action sequentially or will only one action be completed and the others lost? Or what components would u use, within the sopc? Is it enough with one Pipelined bridge ?Honored ContributorNo action will be lost. The mandatory waitrequest signal on the Avalon master interface will freeze 7 masters while the last one will perform its action.
I think the arbitrator uses a more or less round robin system to handle the arbitration, and you can control how many shares each master has if you want some of them to have more frequent access than the others to the slave.Honored ContributorThx Daixiwen,
I still know so less of FPGA but your help is usefull !
