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Altera_Forum
Honored Contributor
Honored ContributorSOPC Generates Failing Paths
Hi all, I generated 8 Master templates (read and write together) and one slave sdram component. When i compile the device gives the warning timing requirements not met. In the timingsadviso...
Altera_ForumHonored Contributor
Honored ContributorNo action will be lost. The mandatory waitrequest signal on the Avalon master interface will freeze 7 masters while the last one will perform its action.
I think the arbitrator uses a more or less round robin system to handle the arbitration, and you can control how many shares each master has if you want some of them to have more frequent access than the others to the slave.
