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Altera_Forum
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15 years ago

SOPC Generates Failing Paths

Hi all, I generated 8 Master templates (read and write together) and one slave sdram component. When i compile the device gives the warning timing requirements not met. In the timingsadviso...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I would put some pipeline bridges into those paths. Perhaps connect four of the masters to on bridge, the other four master to another bridge, then connect those two bridges to the SDRAM controller. If that's not enough then perhaps change the bridge topology slightly. Here is a document that talks about this in more detail: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf