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Honored Contributor
Honored ContributorSOPC Generates Failing Paths
Hi all, I generated 8 Master templates (read and write together) and one slave sdram component. When i compile the device gives the warning timing requirements not met. In the timingsadviso...
Altera_ForumHonored Contributor
Honored ContributorThx Daixiwen,
I still know so less of FPGA but your help is usefull !
