SoPC - VHDL questions

Hi,

I ran into a couple of questions:

I'm building a new component for the SOPC.

It generated a template that seems to me not 'generic' VHDL

entity pio_TERAchip_data is

port (

-- inputs:

signal address : IN STD_LOGIC_VECTOR (1 DOWNTO 0);

signal clk : IN STD_LOGIC;

signal in_port : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

signal reset_n : IN STD_LOGIC;

-- outputs:

signal readdata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

end entity pio_TERAchip_data;

-> Here I haven't seen declaring a signal in a port (like in signal clk : in std_logic;)

Is this the same as:

"clk : in std_logic;"?

2nd question concerns and odd construction (I guess it's a casting, but I'm not sure)

readdata <= std_logic_vector'("00000000000000000000000000000000");

Why this " ' " behind the std_logic_vector? And why this rather diffucult construction?

wasn't it easier to write:

readdata <= (others => '0'); ?

Thanks in advance,

Luc