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Altera_Forum's avatar
Altera_Forum
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17 years ago

SoPC - VHDL questions

Hi, I ran into a couple of questions: I'm building a new component for the SOPC. It generated a template that seems to me not 'generic' VHDL entity pio_TERAchip_data is port ( ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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What's your intention to use a qualified expression in this place? It seems meaningless here.

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As I mentioned, the code is generated by Altera tools. There are many meaningless qualified expressions in the code, but ncsim only complains for "std_logic'('0')" and "std_logic'('1')".

It seems to be legal VHDL code, so I don't understand the warning from Ncsim.