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Altera_Forum's avatar
Altera_Forum
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17 years ago

SoPC - VHDL questions

Hi, I ran into a couple of questions: I'm building a new component for the SOPC. It generated a template that seems to me not 'generic' VHDL entity pio_TERAchip_data is port ( ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Good questions!

The word "signal" in the entity is used to distinguish the port as a signal rather than say a file.

It is assumed to be a signal if omitted, which in 99% of cases that I have seen it usually is!

http://tams-www.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html#concurrent_assertion_statement

Has a great VHDL syntax browser.

As to the type cast attribute question, I have no idea why the template is coded as shown and I agree that your suggested way is much neater. :confused:

Maybe this is something to do with the rules used by the tool-set to automate code generation.

I would be tempted to modify the template to suit your coding style.