Honored Contributor
Honored ContributorI have seen an explanation of the std_logic_vector' thing before as sometimes you see string'("tally ho"). I can't find the explanation I came across but basically it is to explicitly specify the type of your literal e.g. "0000000" could be std_logic_vector or a string. Here obviously there is no doubt as to what type you want but if for example you had some function which was overloaded for string and std_logic_vector then you may need to ensure one or the other was called when you passed in your literal.
Bit of a vague explanation and sorry I can't find the proper reference for you. Basically I wouldn't worry about it and follow vernmid's advice instead. Is this template something that will get frequently updated? If you have automatically generated code from say a state machine editor that gets updated every time you make a change to the state diagram then I'd leave it as it is. If it's just a starting point and you are going to manually maintain the file as you would any other VHDL file then change it so it makes sense to you. (others => '0') is like you suggest a much more generic and maintainable way of writing it.
