some questions about Verilog from beginner:)

Hi everyone!

Just started to learn Verilog language. Meet the problem in my first more or less serious project. Can you explain me please what does -1:0 mean in:

input [input_width-1:0] x;

and what is the difference between this and, for example, input [input_width+2:0] x;

Also would be grateful if someone explains what does DLY_WIDTH means in this code:

(butterworth IIR example):

parameter INPUT_WIDTH = 12;

parameter COEF_WIDTH = 10;

parameter DLY_WIDTH = 18;

parameter F_BITS = 4; // fractional bits

parameter OUTPUT_WIDTH = 21;

parameter L_BIT = 10 ; // low bit

parameter H_BIT = 30; // high bit

// parameter L_BIT = COEF_WIDTH ; // low bit

// parameter H_BIT = L_BIT + OUTPUT_WIDTH - 1; // high bit

//Port Declaration

input clk;

input clken;

input reset;

// input [INPUT_WIDTH-1:0] x;

// output [OUTPUT_WIDTH-1:0] result; //SBF 17.4

input [11:0] x;

output [20:0] result; //SBF 17.4

//Wire Declaration

wire [OUTPUT_WIDTH-1:0] out_biquad1;

wire [F_BITS-1:0] pzeros;

wire [DLY_WIDTH-1:0] xn;

wire [OUTPUT_WIDTH-1:0] result_w;

wire [COEF_WIDTH-1:0] iir_gain;

wire [OUTPUT_WIDTH+COEF_WIDTH-1:0] gain_out;

//Reg Declaration

reg [DLY_WIDTH-1:0] xn_reg;

// reg [OUTPUT_WIDTH-1:0] result;

reg [20:0] result;

reg [DLY_WIDTH-1:0] in_biquad2;

assign pzeros = 0;

assign iir_gain = GAIN;

assign xn = {x[INPUT_WIDTH-1], x[INPUT_WIDTH-1], x[INPUT_WIDTH-1:0], pzeros[F_BITS-1:0]}; // SBF 14.4

Hope you can help me:)

Alex