some questions about Verilog from beginner:)

And just to be clear in case you are real new.

"x" is the name of a signal that come into the chip and [] is telling the code that it is a group of signals, not one signal.

The value 11:0 (as expalined before) means signals named;

x11, x10, x9, ... x1, x0 (12 elements) - so this is a bus or signals into the design, a vector.

You may already get that part - but I though I wold be real complete for you (and others who read this).