some questions about Verilog from beginner:)

INPUT_WIDTH and other parameters are simply constant definitions which allow you to easily manage code in case you need to change the value. If you are familiar with C programming, these are similar to a# define

So, if you have defined INPUT_WIDTH = 12, like in your sample code,

input [INPUT_WIDTH-1:0] x;

is exactly the same as

input [11:0] x;

and [INPUT_WIDTH+2:0] x;

is the same as input [14:0] x;

If you want to change width from 12 to 16, you only modify the parameter line and

you don't need to keep track of all the places where that value is involved.