Forum Discussion
Occasional ContributorSome help with code
Hi,
in principle, there's nothing against designing a pure combinational FPGA, e.g. a binary to seven-segment decoder as shown above.
By design, unregistered combinational logic has output glitches, but that's not necessarily a problem for a seven-segment decoder.
The worst point of the present design is the ineffective way to implement binary to BCD conversion. In an FPGA implementation, look-up table would be the best resource saving solution. Without block RAM, double dabble algorithm can reduce logic cell count.
Apart from ineffective implementation, I don't see a problem with code. It's producing correct output.
If it's intended as HDL learning project, I agree that synchronous design is preferred.
Super ContributorHi,
in principle, there's nothing against designing a pure combinational FPGA, e.g. a binary to seven-segment decoder as shown above.
By design, unregistered combinational logic has output glitches, but that's not necessarily a problem for a seven-segment decoder.
The worst point of the present design is the ineffective way to implement binary to BCD conversion. In an FPGA implementation, look-up table would be the best resource saving solution. Without block RAM, double dabble algorithm can reduce logic cell count.
Apart from ineffective implementation, I don't see a problem with code. It's producing correct output.
If it's intended as HDL learning project, I agree that synchronous design is preferred.
Occasional ContributorThank you for your time.
I listened to roeekalinsky and did everything step by step. Im sure that the design is not the best but after doing some tests it works.
The problem was with the microcontroller, it didnt give the output it should have.
For example i tried a 4 bit output and therefore a 4 bit input on the fpga for a single7 segment display. After doing some tests
i realized that some pins of the microcontroller werent in the right order, or at least it didnt read it in the correct order.
As i said in this example i have a 4 bit output so i said lets try every number from 0 to 9 and display it on the fpga.
So i tried 0000,0001,00010 etc . I dont know why but 0010 gave 4 instead of 2, so i had to make some changes on the pin planner which i find it odd because im sure that they should be in the same order right?
Anyway after some hours i did the right pin assignemed and now works fine. But i tried a bit different method, i seperated the 4 digit number to a 6 bit and a 7 bit output.
