Honored ContributorHi all,
I was used to simulate my project with the simulation tool in earlier version of quartus but now, this tool is no longer available with the version 10.0 and I have to use ModelSim. My questions are : Is there an easy way like "vector waveform file" to initiate the simulation or do I have to do all the stuff with command lines? Do you know a good tutorial to learn how to use ModelSim? Thank you
Honored Contributor
---------------------------------------------------------
-- First part of the testbench file --
---------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
PACKAGE test_project_vhd_tb_types IS
-- input port types
-- output port names
CONSTANT output_test_name : STRING (1 TO 11) := "output_test";
CONSTANT sync_out_name : STRING (1 TO 8) := "sync_out";
-- n(outputs)
CONSTANT o_num : INTEGER := 2;
-- mismatches vector type
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type
SUBTYPE sample_type IS STD_LOGIC;
-- utility functions
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);
END test_project_vhd_tb_types;
PACKAGE BODY test_project_vhd_tb_types IS
FUNCTION std_logic_to_char (a: STD_LOGIC)
RETURN CHARACTER IS
BEGIN
CASE a IS
WHEN 'U' =>
RETURN 'U';
WHEN 'X' =>
RETURN 'X';
WHEN '0' =>
RETURN '0';
WHEN '1' =>
RETURN '1';
WHEN 'Z' =>
RETURN 'Z';
WHEN 'W' =>
RETURN 'W';
WHEN 'L' =>
RETURN 'L';
WHEN 'H' =>
RETURN 'H';
WHEN '-' =>
RETURN 'D';
END CASE;
END;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)
RETURN STRING IS
VARIABLE result : STRING(1 TO a'LENGTH);
VARIABLE j : NATURAL := 1;
BEGIN
FOR i IN a'RANGE LOOP
result(j) := std_logic_to_char(a(i));
j := j + 1;
END LOOP;
RETURN result;
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_to_char(VALUE),JUSTIFIED,field);
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
writeline(output,txt);
write(txt,string'(" Expected value = "));
write(txt,expected_value);
writeline(output,txt);
write(txt,string'(" Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
writeline(output,txt);
write(txt,string'(" Expected value = "));
write(txt,expected_value);
writeline(output,txt);
write(txt,string'(" Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
END test_project_vhd_tb_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.test_project_vhd_tb_types.ALL;
ENTITY test_project_vhd_sample_tst IS
PORT (
master_clock : IN STD_LOGIC;
N : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
sync_in : IN STD_LOGIC;
sampler : OUT sample_type
);
END test_project_vhd_sample_tst;
ARCHITECTURE sample_arch OF test_project_vhd_sample_tst IS
SIGNAL tbo_int_sample_clk : sample_type := '-';
SIGNAL current_time : TIME := 0 ps;
BEGIN
t_prcs_sample : PROCESS ( master_clock , N , sync_in )
BEGIN
IF (NOW > 0 ps) THEN
IF (NOW > 0 ps) AND (NOW /= current_time) THEN
IF (tbo_int_sample_clk = '-') THEN
tbo_int_sample_clk <= '0';
ELSE
tbo_int_sample_clk <= NOT tbo_int_sample_clk ;
END IF;
END IF;
current_time <= NOW;
END IF;
END PROCESS t_prcs_sample;
sampler <= tbo_int_sample_clk;
END sample_arch;
-------------------------------------------------------------------
-- First Part of the testbench file page2 --
--------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.test_project_vhd_tb_types.ALL;
ENTITY test_project_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
output_test : IN STD_LOGIC;
sync_out : IN STD_LOGIC;
sampler : IN sample_type
);
END test_project_vhd_check_tst;
ARCHITECTURE ovec_arch OF test_project_vhd_check_tst IS
SIGNAL output_test_expected,output_test_expected_prev,output_test_prev : STD_LOGIC;
SIGNAL sync_out_expected,sync_out_expected_prev,sync_out_prev : STD_LOGIC;
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
output_test_expected_prev <= output_test_expected;
sync_out_expected_prev <= sync_out_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
output_test_prev <= output_test;
sync_out_prev <= sync_out;
END PROCESS t_prcs_update_o_real_hist;
-- expected sync_out
t_prcs_sync_out: PROCESS
BEGIN
sync_out_expected <= 'X';
WAIT;
END PROCESS t_prcs_sync_out;
-- expected output_test
t_prcs_output_test: PROCESS
BEGIN
output_test_expected <= 'X';
WAIT;
END PROCESS t_prcs_output_test;
-- Set trigger on real/expected o/ pattern changes
t_prcs_trigger_e : PROCESS(output_test_expected,sync_out_expected)
BEGIN
trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;
t_prcs_trigger_r : PROCESS(output_test,sync_out)
BEGIN
trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;
t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;
VARIABLE last_output_test_exp : STD_LOGIC := 'U';
VARIABLE last_sync_out_exp : STD_LOGIC := 'U';
VARIABLE on_first_change : trackvec := "11";
BEGIN
WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
AND sampler'EVENT;
IF (debug_tbench = '1') THEN
write(txt,string'("Scanning pattern "));
write(txt,i);
writeline(output,txt);
write(txt,string'("| expected "));write(txt,output_test_name);write(txt,string'(" = "));write(txt,output_test_expected_prev);
write(txt,string'("| expected "));write(txt,sync_out_name);write(txt,string'(" = "));write(txt,sync_out_expected_prev);
writeline(output,txt);
write(txt,string'("| real "));write(txt,output_test_name);write(txt,string'(" = "));write(txt,output_test_prev);
write(txt,string'("| real "));write(txt,sync_out_name);write(txt,string'(" = "));write(txt,sync_out_prev);
writeline(output,txt);
i := i + 1;
END IF;
IF ( output_test_expected_prev /= 'X' ) AND (output_test_expected_prev /= 'U' ) AND (output_test_prev /= output_test_expected_prev) AND (
(output_test_expected_prev /= last_output_test_exp) OR
(on_first_change(1) = '1')
) THEN
throw_error("output_test",output_test_expected_prev,output_test_prev);
num_mismatches(0) <= num_mismatches(0) + 1;
on_first_change(1) := '0';
last_output_test_exp := output_test_expected_prev;
END IF;
IF ( sync_out_expected_prev /= 'X' ) AND (sync_out_expected_prev /= 'U' ) AND (sync_out_prev /= sync_out_expected_prev) AND (
(sync_out_expected_prev /= last_sync_out_exp) OR
(on_first_change(2) = '1')
) THEN
throw_error("sync_out",sync_out_expected_prev,sync_out_prev);
num_mismatches(1) <= num_mismatches(1) + 1;
on_first_change(2) := '0';
last_sync_out_exp := sync_out_expected_prev;
END IF;
trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;
t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;
t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 1000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1);
IF (total_mismatches = 0) THEN
write(txt,string'("Simulation passed !"));
writeline(output,txt);
ELSE
write(txt,total_mismatches);
write(txt,string'(" mismatched vectors : Simulation failed !"));
writeline(output,txt);
END IF;
WAIT;
END PROCESS t_prcs_endsim;
END ovec_arch;
---------------------------------------------------------
-- Second part of the testbench file --
---------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.test_project_vhd_tb_types.ALL;
ENTITY test_project_vhd_vec_tst IS
END test_project_vhd_vec_tst;
ARCHITECTURE test_project_arch OF test_project_vhd_vec_tst IS
-- constants
-- signals
SIGNAL master_clock : STD_LOGIC;
SIGNAL N : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL output_test : STD_LOGIC;
SIGNAL sync_in : STD_LOGIC;
SIGNAL sync_out : STD_LOGIC;
SIGNAL sampler : sample_type;
COMPONENT test_project
PORT (
master_clock : IN STD_LOGIC;
N : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
output_test : OUT STD_LOGIC;
sync_in : IN STD_LOGIC;
sync_out : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT test_project_vhd_check_tst
PORT (
output_test : IN STD_LOGIC;
sync_out : IN STD_LOGIC;
sampler : IN sample_type
);
END COMPONENT;
COMPONENT test_project_vhd_sample_tst
PORT (
master_clock : IN STD_LOGIC;
N : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
sync_in : IN STD_LOGIC;
sampler : OUT sample_type
);
END COMPONENT;
BEGIN
i1 : test_project
PORT MAP (
-- list connections between master ports and signals
master_clock => master_clock,
N => N,
output_test => output_test,
sync_in => sync_in,
sync_out => sync_out
);
-- master_clock
t_prcs_master_clock: PROCESS
BEGIN
LOOP
master_clock <= '0';
WAIT FOR 5000 ps;
master_clock <= '1';
WAIT FOR 5000 ps;
IF (NOW >= 1000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_master_clock;
-- N
t_prcs_N_31: PROCESS
BEGIN
N(31) <= '0';
WAIT;
END PROCESS t_prcs_N_31;
-- N
t_prcs_N_30: PROCESS
BEGIN
N(30) <= '0';
WAIT;
END PROCESS t_prcs_N_30;
-- N
t_prcs_N_29: PROCESS
BEGIN
N(29) <= '0';
WAIT;
END PROCESS t_prcs_N_29;
-- N
t_prcs_N_28: PROCESS
BEGIN
N(28) <= '0';
WAIT;
END PROCESS t_prcs_N_28;
-- N
t_prcs_N_27: PROCESS
BEGIN
N(27) <= '0';
WAIT;
END PROCESS t_prcs_N_27;
-- N
t_prcs_N_26: PROCESS
BEGIN
N(26) <= '0';
WAIT;
END PROCESS t_prcs_N_26;
-- N
t_prcs_N_25: PROCESS
BEGIN
N(25) <= '0';
WAIT;
END PROCESS t_prcs_N_25;
-- N
t_prcs_N_24: PROCESS
BEGIN
N(24) <= '0';
WAIT;
END PROCESS t_prcs_N_24;
-- N
t_prcs_N_23: PROCESS
BEGIN
N(23) <= '0';
WAIT;
END PROCESS t_prcs_N_23;
-- N
t_prcs_N_22: PROCESS
BEGIN
N(22) <= '0';
WAIT;
END PROCESS t_prcs_N_22;
-- N
t_prcs_N_21: PROCESS
BEGIN
N(21) <= '0';
WAIT;
END PROCESS t_prcs_N_21;
-- N
t_prcs_N_20: PROCESS
BEGIN
N(20) <= '0';
WAIT;
END PROCESS t_prcs_N_20;
-- N
t_prcs_N_19: PROCESS
BEGIN
N(19) <= '0';
WAIT;
END PROCESS t_prcs_N_19;
-- N
t_prcs_N_18: PROCESS
BEGIN
N(18) <= '0';
WAIT;
END PROCESS t_prcs_N_18;
-- N
t_prcs_N_17: PROCESS
BEGIN
N(17) <= '0';
WAIT;
END PROCESS t_prcs_N_17;
-- N
t_prcs_N_16: PROCESS
BEGIN
N(16) <= '0';
WAIT;
END PROCESS t_prcs_N_16;
-- N
t_prcs_N_15: PROCESS
BEGIN
N(15) <= '0';
WAIT;
END PROCESS t_prcs_N_15;
-- N
t_prcs_N_14: PROCESS
BEGIN
N(14) <= '0';
WAIT;
END PROCESS t_prcs_N_14;
-- N
t_prcs_N_13: PROCESS
BEGIN
N(13) <= '0';
WAIT;
END PROCESS t_prcs_N_13;
-- N
t_prcs_N_12: PROCESS
BEGIN
N(12) <= '0';
WAIT;
END PROCESS t_prcs_N_12;
-- N
t_prcs_N_11: PROCESS
BEGIN
N(11) <= '0';
WAIT;
END PROCESS t_prcs_N_11;
-- N
t_prcs_N_10: PROCESS
BEGIN
N(10) <= '0';
WAIT;
END PROCESS t_prcs_N_10;
-- N
t_prcs_N_9: PROCESS
BEGIN
N(9) <= '0';
WAIT;
END PROCESS t_prcs_N_9;
-- N
t_prcs_N_8: PROCESS
BEGIN
N(8) <= '0';
WAIT;
END PROCESS t_prcs_N_8;
-- N
t_prcs_N_7: PROCESS
BEGIN
N(7) <= '0';
WAIT;
END PROCESS t_prcs_N_7;
-- N
t_prcs_N_6: PROCESS
BEGIN
N(6) <= '0';
WAIT;
END PROCESS t_prcs_N_6;
-- N
t_prcs_N_5: PROCESS
BEGIN
N(5) <= '1';
WAIT;
END PROCESS t_prcs_N_5;
-- N
t_prcs_N_4: PROCESS
BEGIN
N(4) <= '1';
WAIT;
END PROCESS t_prcs_N_4;
-- N
t_prcs_N_3: PROCESS
BEGIN
N(3) <= '0';
WAIT;
END PROCESS t_prcs_N_3;
-- N
t_prcs_N_2: PROCESS
BEGIN
N(2) <= '1';
WAIT;
END PROCESS t_prcs_N_2;
-- N
t_prcs_N_1: PROCESS
BEGIN
N(1) <= '0';
WAIT;
END PROCESS t_prcs_N_1;
-- N
t_prcs_N_0: PROCESS
BEGIN
N(0) <= '0';
WAIT;
END PROCESS t_prcs_N_0;
-- sync_in
t_prcs_sync_in: PROCESS
BEGIN
sync_in <= '1';
WAIT FOR 7000 ps;
FOR i IN 1 TO 9
LOOP
sync_in <= '0';
WAIT FOR 50000 ps;
sync_in <= '1';
WAIT FOR 50000 ps;
END LOOP;
sync_in <= '0';
WAIT FOR 50000 ps;
sync_in <= '1';
WAIT;
END PROCESS t_prcs_sync_in;
tb_sample : test_project_vhd_sample_tst
PORT MAP (
master_clock => master_clock,
N => N,
sync_in => sync_in,
sampler => sampler
);
tb_out : test_project_vhd_check_tst
PORT MAP (
output_test => output_test,
sync_out => sync_out,
sampler => sampler
);
END test_project_arch;
That stuff at the beginning of the text file is defining a load of procedures that write different types out to a file. Any generated code tends to have a load of stuff that probably be hidden away in a package if you wrote it yourself.
Honored ContributorHi,
How did you convert the simulation file from a .wvf file to a testbench HDL file?
