---------------------------------------------------------
-- Second part of the testbench file --
---------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.test_project_vhd_tb_types.ALL;
ENTITY test_project_vhd_vec_tst IS
END test_project_vhd_vec_tst;
ARCHITECTURE test_project_arch OF test_project_vhd_vec_tst IS
-- constants
-- signals
SIGNAL master_clock : STD_LOGIC;
SIGNAL N : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL output_test : STD_LOGIC;
SIGNAL sync_in : STD_LOGIC;
SIGNAL sync_out : STD_LOGIC;
SIGNAL sampler : sample_type;
COMPONENT test_project
PORT (
master_clock : IN STD_LOGIC;
N : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
output_test : OUT STD_LOGIC;
sync_in : IN STD_LOGIC;
sync_out : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT test_project_vhd_check_tst
PORT (
output_test : IN STD_LOGIC;
sync_out : IN STD_LOGIC;
sampler : IN sample_type
);
END COMPONENT;
COMPONENT test_project_vhd_sample_tst
PORT (
master_clock : IN STD_LOGIC;
N : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
sync_in : IN STD_LOGIC;
sampler : OUT sample_type
);
END COMPONENT;
BEGIN
i1 : test_project
PORT MAP (
-- list connections between master ports and signals
master_clock => master_clock,
N => N,
output_test => output_test,
sync_in => sync_in,
sync_out => sync_out
);
-- master_clock
t_prcs_master_clock: PROCESS
BEGIN
LOOP
master_clock <= '0';
WAIT FOR 5000 ps;
master_clock <= '1';
WAIT FOR 5000 ps;
IF (NOW >= 1000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_master_clock;
-- N
t_prcs_N_31: PROCESS
BEGIN
N(31) <= '0';
WAIT;
END PROCESS t_prcs_N_31;
-- N
t_prcs_N_30: PROCESS
BEGIN
N(30) <= '0';
WAIT;
END PROCESS t_prcs_N_30;
-- N
t_prcs_N_29: PROCESS
BEGIN
N(29) <= '0';
WAIT;
END PROCESS t_prcs_N_29;
-- N
t_prcs_N_28: PROCESS
BEGIN
N(28) <= '0';
WAIT;
END PROCESS t_prcs_N_28;
-- N
t_prcs_N_27: PROCESS
BEGIN
N(27) <= '0';
WAIT;
END PROCESS t_prcs_N_27;
-- N
t_prcs_N_26: PROCESS
BEGIN
N(26) <= '0';
WAIT;
END PROCESS t_prcs_N_26;
-- N
t_prcs_N_25: PROCESS
BEGIN
N(25) <= '0';
WAIT;
END PROCESS t_prcs_N_25;
-- N
t_prcs_N_24: PROCESS
BEGIN
N(24) <= '0';
WAIT;
END PROCESS t_prcs_N_24;
-- N
t_prcs_N_23: PROCESS
BEGIN
N(23) <= '0';
WAIT;
END PROCESS t_prcs_N_23;
-- N
t_prcs_N_22: PROCESS
BEGIN
N(22) <= '0';
WAIT;
END PROCESS t_prcs_N_22;
-- N
t_prcs_N_21: PROCESS
BEGIN
N(21) <= '0';
WAIT;
END PROCESS t_prcs_N_21;
-- N
t_prcs_N_20: PROCESS
BEGIN
N(20) <= '0';
WAIT;
END PROCESS t_prcs_N_20;
-- N
t_prcs_N_19: PROCESS
BEGIN
N(19) <= '0';
WAIT;
END PROCESS t_prcs_N_19;
-- N
t_prcs_N_18: PROCESS
BEGIN
N(18) <= '0';
WAIT;
END PROCESS t_prcs_N_18;
-- N
t_prcs_N_17: PROCESS
BEGIN
N(17) <= '0';
WAIT;
END PROCESS t_prcs_N_17;
-- N
t_prcs_N_16: PROCESS
BEGIN
N(16) <= '0';
WAIT;
END PROCESS t_prcs_N_16;
-- N
t_prcs_N_15: PROCESS
BEGIN
N(15) <= '0';
WAIT;
END PROCESS t_prcs_N_15;
-- N
t_prcs_N_14: PROCESS
BEGIN
N(14) <= '0';
WAIT;
END PROCESS t_prcs_N_14;
-- N
t_prcs_N_13: PROCESS
BEGIN
N(13) <= '0';
WAIT;
END PROCESS t_prcs_N_13;
-- N
t_prcs_N_12: PROCESS
BEGIN
N(12) <= '0';
WAIT;
END PROCESS t_prcs_N_12;
-- N
t_prcs_N_11: PROCESS
BEGIN
N(11) <= '0';
WAIT;
END PROCESS t_prcs_N_11;
-- N
t_prcs_N_10: PROCESS
BEGIN
N(10) <= '0';
WAIT;
END PROCESS t_prcs_N_10;
-- N
t_prcs_N_9: PROCESS
BEGIN
N(9) <= '0';
WAIT;
END PROCESS t_prcs_N_9;
-- N
t_prcs_N_8: PROCESS
BEGIN
N(8) <= '0';
WAIT;
END PROCESS t_prcs_N_8;
-- N
t_prcs_N_7: PROCESS
BEGIN
N(7) <= '0';
WAIT;
END PROCESS t_prcs_N_7;
-- N
t_prcs_N_6: PROCESS
BEGIN
N(6) <= '0';
WAIT;
END PROCESS t_prcs_N_6;
-- N
t_prcs_N_5: PROCESS
BEGIN
N(5) <= '1';
WAIT;
END PROCESS t_prcs_N_5;
-- N
t_prcs_N_4: PROCESS
BEGIN
N(4) <= '1';
WAIT;
END PROCESS t_prcs_N_4;
-- N
t_prcs_N_3: PROCESS
BEGIN
N(3) <= '0';
WAIT;
END PROCESS t_prcs_N_3;
-- N
t_prcs_N_2: PROCESS
BEGIN
N(2) <= '1';
WAIT;
END PROCESS t_prcs_N_2;
-- N
t_prcs_N_1: PROCESS
BEGIN
N(1) <= '0';
WAIT;
END PROCESS t_prcs_N_1;
-- N
t_prcs_N_0: PROCESS
BEGIN
N(0) <= '0';
WAIT;
END PROCESS t_prcs_N_0;
-- sync_in
t_prcs_sync_in: PROCESS
BEGIN
sync_in <= '1';
WAIT FOR 7000 ps;
FOR i IN 1 TO 9
LOOP
sync_in <= '0';
WAIT FOR 50000 ps;
sync_in <= '1';
WAIT FOR 50000 ps;
END LOOP;
sync_in <= '0';
WAIT FOR 50000 ps;
sync_in <= '1';
WAIT;
END PROCESS t_prcs_sync_in;
tb_sample : test_project_vhd_sample_tst
PORT MAP (
master_clock => master_clock,
N => N,
sync_in => sync_in,
sampler => sampler
);
tb_out : test_project_vhd_check_tst
PORT MAP (
output_test => output_test,
sync_out => sync_out,
sampler => sampler
);
END test_project_arch;
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