-------------------------------------------------------------------
-- First Part of the testbench file page2 --
--------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.test_project_vhd_tb_types.ALL;
ENTITY test_project_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
output_test : IN STD_LOGIC;
sync_out : IN STD_LOGIC;
sampler : IN sample_type
);
END test_project_vhd_check_tst;
ARCHITECTURE ovec_arch OF test_project_vhd_check_tst IS
SIGNAL output_test_expected,output_test_expected_prev,output_test_prev : STD_LOGIC;
SIGNAL sync_out_expected,sync_out_expected_prev,sync_out_prev : STD_LOGIC;
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
output_test_expected_prev <= output_test_expected;
sync_out_expected_prev <= sync_out_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
output_test_prev <= output_test;
sync_out_prev <= sync_out;
END PROCESS t_prcs_update_o_real_hist;
-- expected sync_out
t_prcs_sync_out: PROCESS
BEGIN
sync_out_expected <= 'X';
WAIT;
END PROCESS t_prcs_sync_out;
-- expected output_test
t_prcs_output_test: PROCESS
BEGIN
output_test_expected <= 'X';
WAIT;
END PROCESS t_prcs_output_test;
-- Set trigger on real/expected o/ pattern changes
t_prcs_trigger_e : PROCESS(output_test_expected,sync_out_expected)
BEGIN
trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;
t_prcs_trigger_r : PROCESS(output_test,sync_out)
BEGIN
trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;
t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;
VARIABLE last_output_test_exp : STD_LOGIC := 'U';
VARIABLE last_sync_out_exp : STD_LOGIC := 'U';
VARIABLE on_first_change : trackvec := "11";
BEGIN
WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
AND sampler'EVENT;
IF (debug_tbench = '1') THEN
write(txt,string'("Scanning pattern "));
write(txt,i);
writeline(output,txt);
write(txt,string'("| expected "));write(txt,output_test_name);write(txt,string'(" = "));write(txt,output_test_expected_prev);
write(txt,string'("| expected "));write(txt,sync_out_name);write(txt,string'(" = "));write(txt,sync_out_expected_prev);
writeline(output,txt);
write(txt,string'("| real "));write(txt,output_test_name);write(txt,string'(" = "));write(txt,output_test_prev);
write(txt,string'("| real "));write(txt,sync_out_name);write(txt,string'(" = "));write(txt,sync_out_prev);
writeline(output,txt);
i := i + 1;
END IF;
IF ( output_test_expected_prev /= 'X' ) AND (output_test_expected_prev /= 'U' ) AND (output_test_prev /= output_test_expected_prev) AND (
(output_test_expected_prev /= last_output_test_exp) OR
(on_first_change(1) = '1')
) THEN
throw_error("output_test",output_test_expected_prev,output_test_prev);
num_mismatches(0) <= num_mismatches(0) + 1;
on_first_change(1) := '0';
last_output_test_exp := output_test_expected_prev;
END IF;
IF ( sync_out_expected_prev /= 'X' ) AND (sync_out_expected_prev /= 'U' ) AND (sync_out_prev /= sync_out_expected_prev) AND (
(sync_out_expected_prev /= last_sync_out_exp) OR
(on_first_change(2) = '1')
) THEN
throw_error("sync_out",sync_out_expected_prev,sync_out_prev);
num_mismatches(1) <= num_mismatches(1) + 1;
on_first_change(2) := '0';
last_sync_out_exp := sync_out_expected_prev;
END IF;
trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;
t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;
t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 1000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1);
IF (total_mismatches = 0) THEN
write(txt,string'("Simulation passed !"));
writeline(output,txt);
ELSE
write(txt,total_mismatches);
write(txt,string'(" mismatched vectors : Simulation failed !"));
writeline(output,txt);
END IF;
WAIT;
END PROCESS t_prcs_endsim;
END ovec_arch;
Honored Contributor
