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Altera_Forum
Honored Contributor
Honored ContributorSimple Delay in VHDL (sanity check)
Hi,
Anyone availible to help me with a quick sanity check :) . I created a simple delay in vhdl. My testbech offers an input clock with 40ns period and 50% duty cycle so plently of time to allow the required transitions. The problem is that when i run the simulation clk_out doesnt make any transitions at all. This must be a simple mistake but i cannot see it.library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY clk_delay IS
PORT ( clk_in : IN STD_LOGIC;
clk_out : OUT STD_LOGIC);
END clk_delay;
ARCHITECTURE behav OF clk_delay IS
BEGIN
P1: PROCESS (clk_in)
BEGIN
IF clk_in'EVENT AND clk_in = '1' THEN
clk_out <= clk_in AFTER 5ns;
END IF;
END PROCESS;
END behav;5 Replies
Altera_Forum--- Quote Start --- thanks for the quick response. I have modelsim i will install and try it. From the code i posted, do you agree that if clk_out were mapped to a pin and measured with a scope it would essentially by the same as clk_in with the 5ns delay (and obivously taking into account any timing issues in the fitting process). regards. --- Quote End --- No, even in simulation this would not be the case. Because clk_out would always be '1' because there's only an assignment if clk_in = '1'. So if you want a delayed clock, use an PLL (preferred, deterministic) or just use clk_out <= clk_in without the if....statement and depend on the path dalay (not preferred, not deterministic) Success, Ton- Altera_Forum
>No
>Delays cannot be compiled in quartus. >You have to use a Phase lock loop and >move the clk_out 45 degrees out of phase wrt clk_in. I would be even more specific. Delays cannot be synthesized with VHDL or Verilog code. You can simulate a delay. You cannot generate a circuit with a given delay. - Altera_Forum--- Quote Start --- thanks for the quick response. I have modelsim i will install and try it. From the code i posted, do you agree that if clk_out were mapped to a pin and measured with a scope it would essentially by the same as clk_in with the 5ns delay (and obivously taking into account any timing issues in the fitting process). regards. --- Quote End --- No Delays cannot be compiled in quartus. You have to use a Phase lock loop and move the clk_out 45 degrees out of phase wrt clk_in.
- Altera_Forum
thanks for the quick response.
I have modelsim i will install and try it. From the code i posted, do you agree that if clk_out were mapped to a pin and measured with a scope it would essentially by the same as clk_in with the 5ns delay (and obivously taking into account any timing issues in the fitting process). regards. - Altera_Forum
Quartus simulator doesnt support this kind of behavioural code because it simulates post synthesis netlists. You cannot synthesise delays.
The output you get will just be a registered version of your clock, which will always be the same value. You will have to use modelsim to see this.
