Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- thanks for the quick response. I have modelsim i will install and try it. From the code i posted, do you agree that if clk_out were mapped to a pin and measured with a scope it would essentially by the same as clk_in with the 5ns delay (and obivously taking into account any timing issues in the fitting process). regards. --- Quote End --- No, even in simulation this would not be the case. Because clk_out would always be '1' because there's only an assignment if clk_in = '1'. So if you want a delayed clock, use an PLL (preferred, deterministic) or just use clk_out <= clk_in without the if....statement and depend on the path dalay (not preferred, not deterministic) Success, Ton