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Altera_Forum
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15 years ago

Simple Delay in VHDL (sanity check)

Hi, Anyone availible to help me with a quick sanity check :) . I created a simple delay in vhdl. My testbech offers an input clock with 40ns period and 50% duty cycle so plently of tim...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Quartus simulator doesnt support this kind of behavioural code because it simulates post synthesis netlists. You cannot synthesise delays.

The output you get will just be a registered version of your clock, which will always be the same value.

You will have to use modelsim to see this.