Simple Delay in VHDL (sanity check)

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thanks for the quick response.

I have modelsim i will install and try it.

From the code i posted, do you agree that if clk_out were mapped to a pin and measured with a scope it would essentially by the same as clk_in with the 5ns delay (and obivously taking into account any timing issues in the fitting process).

regards.

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No

Delays cannot be compiled in quartus. You have to use a Phase lock loop and move the clk_out 45 degrees out of phase wrt clk_in.