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Honored Contributor
Honored ContributorSimple Delay in VHDL (sanity check)
Hi, Anyone availible to help me with a quick sanity check :) . I created a simple delay in vhdl. My testbech offers an input clock with 40ns period and 50% duty cycle so plently of tim...
Altera_ForumHonored Contributor
Honored Contributor>No
>Delays cannot be compiled in quartus. >You have to use a Phase lock loop and >move the clk_out 45 degrees out of phase wrt clk_in. I would be even more specific. Delays cannot be synthesized with VHDL or Verilog code. You can simulate a delay. You cannot generate a circuit with a given delay.
