Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
It means, that you have to enable the SignalTyp II instance before compiling the design. The error can also indicate, that you haven't downloaded the recent FPGA image.
- Altera_Forum
Honored Contributor
Thanks for your reply!
I download the *.jic file befor run signaltap analysis, then shows the error. Because I want to capture the online data. But when I download the *.sof file, then capture the data, there have no error. Why? - Altera_Forum
Honored Contributor
--- Quote Start --- But when I download the *.sof file, then capture the data, there have no error. Why? --- Quote End --- I guess, it's a different design.*.jic has to be generated manually, unless you have written scripts that make it after compilation.