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sRama28's avatar
sRama28
Icon for New Contributor rankNew Contributor
5 years ago

signal type not available in QSYS

hi

i have porting one board from CYCLONE to MAX 10.

in my design contain ADC interface then the data will transfer to NIOS through DMA.

so we have created some control signal to do handshake between FPGA and NIOS.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec_1_3.pdf

referred this document which has one signal dataavilable. whenever my FIFO having data which will trigger the signal to NIOS then the NIOS will read it.

but now i m using QUARTS 15.0 where data available signal is not available in avalon memory map interface .

so what is the replacement signal for that.

PROCESS FLOW:

1.dataavilable will go to NIOS from FPGA [need alternate signal for this]

Avalon interface document [2010 edition]-3.5.4.4 section flow control .

2.read signal will reach FPGA from NIOS.[this is available]

Reply me INTEL please

6 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    That signal has been deprecated from the Avalon memory-mapped standard. I don't know what FIFO IP you are using or if you are building your own, but usually there would be a "not empty" signal or a status register to read to see if data is available.

    If you use Avalon streaming instead of memory-mapped, you can make use of the valid and ready signals that are part of that standard for data streaming in and out of the FIFO.

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    5 years ago

    Hi @sRama28,

    Hope this message find you well, please do let if the issues still persist, and we would be more than happy to look into it or any other clarification that we can help you with.

    Warm regards.

    • sRama28's avatar
      sRama28
      Icon for New Contributor rankNew Contributor
      5 years ago

      hi Intel

      1.not empty signal is not available in avalon memory mapped slave interface.

      2.status register method - means using PIO register and writing the value to 1 after FPGA FIFO got data.please confirm these point.

      we need below signals in avalon memory mapped slave interface

      1.chip select

      2.read enable

      3.read data

      4.data available /not empty/status register concept[please explain]