ContributionsMost RecentMost LikesSolutionsethernet timeout max 10 with nichistack SRAM memory hi Intel using MAX10 FPGA with TSE MAC ,SRAM and own application as client every time need to below steps 1.open connection from client and connected to server. 2.client will get (4500 in 40 times )data from MAX 10 NIOS processor . 3.close the connection and again re-open the connection . using SRAM [tristate controller ]for Stack ,heap and code ,packet memory. i am getting frequent time out in one hour . but my setup as to run for long hours minimum 1 day. listed observation when timeout times: 1.processor is going for dtrap and panic ,MAC close 2.no sync ,ack fin reply from processor [Processor is in hold state may be] Note : if i added some delay after data send it is running for 2 -3 hours then getting timeout and errors . really worried on this more than 2 months but not able to find solution for this project .help to resolve the problem and find the route cause for this. if someone helped me it will be grate help for us team. Regards Ram. Re: NIOS SRAM memory corruption check any update on this intel guys .. NIOS SRAM memory corruption check hi intel need answer for below. 1.how to find heap and stack starting and ending address. heap_start and stack base adress are same in objectdumb file .is it right? 2.how to check stack growing and corrupting program lines in SRAM .suggest any memory corruption check method? 3.if i created RTOS task after the task execution stack pointer is pointing bss section of code .is it right behavior or sp always within the limit of stack memory? 4.if i added any breakpoints code behavior is changing getting failure in ethernet driver files what is the reason? Re: signal type not available in QSYS hi Intel 1.not empty signal is not available in avalon memory mapped slave interface. 2.status register method - means using PIO register and writing the value to 1 after FPGA FIFO got data.please confirm these point. we need below signals in avalon memory mapped slave interface 1.chip select 2.read enable 3.read data 4.data available /not empty/status register concept[please explain] signal type not available in QSYS hi i have porting one board from CYCLONE to MAX 10. in my design contain ADC interface then the data will transfer to NIOS through DMA. so we have created some control signal to do handshake between FPGA and NIOS. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec_1_3.pdf referred this document which has one signal dataavilable. whenever my FIFO having data which will trigger the signal to NIOS then the NIOS will read it. but now i m using QUARTS 15.0 where data available signal is not available in avalon memory map interface . so what is the replacement signal for that. PROCESS FLOW: 1.dataavilable will go to NIOS from FPGA [need alternate signal for this] Avalon interface document [2010 edition]-3.5.4.4 section flow control . 2.read signal will reach FPGA from NIOS.[this is available] Reply me INTEL please Re: Nios II exception handler hi i am using MAX10 FPGA with PHY 88E1111 phy IC for ethenet connection with SRAM memory [4MB]. when running code NIOS is breaking at getting cause value is 5 in debugger . Also sometimes hang in running mode and restarting the NIOS . Q1. what is the route cause for this issue? Q2.how to solve these exception ? Q3.anything i want to change in my BSP settings or QSYS file? please help me to resolve the issue quickly.. Re: MAX10 with parallel flash chipNO .i want to know is it possible to boot NIOS from external IO flash using srec file .? NOT EPCS and MICRON FLASH.max 10 ethernet -remote update hi i m developing code for MAX 10 internal CFM memory update through Ethernet RPD file. Q1.can you share me any utility to browse and send the file.? Q2.from google i have got an 429 application software shall i use it for my update? (but it is not opening properly) please respond ASAP MAX10 with parallel flash chip is it possible to boot NIOS processor in MAX 10 FPGA with Parallel flash chip (adding tristate controller IP in QSYS) ? i know EPCS or UFM memory is possible but i want to know the external flash is possible or not .please confirm? NIOS-not booting UFM with simple socker server i have used MAX 10 FPGA with NIOS processor and sample simple socket server code. refered AN730 document and tried 1a method and loded code into CFM and UFM memory of MAX 10. But if I restart the board nios is not booting .please help me to boot NIOS in MAX10.