New Contributor
ModeratorHi @sRama28,
Hope this message find you well, please do let if the issues still persist, and we would be more than happy to look into it or any other clarification that we can help you with.
Warm regards.
New Contributorhi Intel
1.not empty signal is not available in avalon memory mapped slave interface.
2.status register method - means using PIO register and writing the value to 1 after FPGA FIFO got data.please confirm these point.
we need below signals in avalon memory mapped slave interface
1.chip select
2.read enable
3.read data
4.data available /not empty/status register concept[please explain]
ModeratorHi @sRama28,
Apologies for the long wait and thank you for your patients.
Back to the initial question you have on the replacement for dataavailable signals, alternatively we woudl recommend to use the Avalon streaming as mention.
Attached is the user guide on how to implement the ADC on Max 10 devices.
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_adc.pdf
Warm regards.
ModeratorHi @sRama28,
Just to add on, for the second part of the question, the 'not ready signals' is readily available in the Avalon-st
As for the second part of the question, more details of the signals as explained below:
- chip select (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf#page=67&zoom=100,0,0)
- read enable ((https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf#page=67&zoom=100,0,0))
- read data (signal available in avalon-mm and are required)
- data available (as mention has been deprecated, recommends using avalon-st)
Warm regards.
