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sRama28's avatar
sRama28
Icon for New Contributor rankNew Contributor
5 years ago

signal type not available in QSYS

hi i have porting one board from CYCLONE to MAX 10. in my design contain ADC interface then the data will transfer to NIOS through DMA. so we have created some control signal to do handshake ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

That signal has been deprecated from the Avalon memory-mapped standard. I don't know what FIFO IP you are using or if you are building your own, but usually there would be a "not empty" signal or a status register to read to see if data is available.

If you use Avalon streaming instead of memory-mapped, you can make use of the valid and ready signals that are part of that standard for data streaming in and out of the FIFO.