Sharing memory: Nios and HDL-module

Hi All!

I need to share SRAM between nios II and HDL-module. What component I need in SOPC? I have a hand-made component Bridge to SRAM (MM slave- MM tristate master) and MM Tristate slave component of SRAM. SRAM in CPU working well. But I can't to connect HDL to SRAM-Bridge in quartus (some error). What is wrong?

Error: Net "CLOCK_50", which fans out to "addr_for_write[0]", cannot be assigned more than one value

Error: Net is fed by "nios:DUT|bridge_2_sram_writen"

Error: Net is fed by "CLOCK_50"

Code of top-level

module DE2_115_CAMERA
   CLOCK2_50,
   ////////////////////	SRAM Interface		////////////////
   SRAM_DQ, //	SRAM Data    bus 16 Bits
   SRAM_ADDR, //	SRAM Address bus 18 Bits
   SRAM_UB_N, //	SRAM High-byte Data Mask 
   SRAM_LB_N, //	SRAM Low-byte Data Mask 
   SRAM_WE_N, //	SRAM Write Enable
   SRAM_CE_N,//	SRAM Chip Enable
   SRAM_OE_N, //	SRAM Output Enable
...	
);
input       	CLOCK_50;
////////////////////////	SRAM Interface	////////////////////////
inout		SRAM_DQ;
output		SRAM_ADDR;
output		SRAM_UB_N;
output		SRAM_LB_N;
output		SRAM_WE_N;
output		SRAM_CE_N;
output		SRAM_OE_N;
....
nios DUT(
.clk_0 (CLOCK_50),
// SRAM 
.bridge_2_sram_address     (SRAM_ADDR),
.bridge_2_sram_byteenablen ({SRAM_UB_N, SRAM_LB_N}),
.bridge_2_sram_data        (SRAM_DQ),
.bridge_2_sram_writen      (SRAM_WE_N),		
...
);
reg  pixcount;
reg addr_for_write;
reg  colour;
// fill  first 640 item of SRAM
always @(posedge CLOCK_50)
begin
   if (!KEY)	
   begin		
      colour <= 16'h00ff;
      pixcount <= 0;
   end
   else
   begin	
      if (pixcount < 640)
      begin
         addr_for_write <= pixcount;
         pixcount <= pixcount + 1;
      end			
      else
      begin		
         addr_for_write <= 20'hzzzzz;			
         colour <= 16'hzzzzz;		
      end		
   end
end
assign SRAM_ADDR = addr_for_write;
assign SRAM_DQ = colour;