Sharing memory: Nios and HDL-module

If I correctly understood, your sram is accessed both by the above nios:DUT module and by Nios II processor through a tristate bridge.

You can't connect two tristate masters to a single tristate device.

Each master would drive the same signals thus causing bus contention.

This is possible only if you have arbitration logic for regulating bus accesses, namely holding one of the masters while the other is accessing the bus. AFAIK this function is not provided by the Avalon tristate bridge.

You must use a single tristate bridge and design your module as an Avalon master, so you can connect it before the ts bridge.