set_input_delay And set_output_delay .SDC Constraints

Hello! I have little familiarity with the set_input_delay and set_output_delay SDC and was wondering whether the following commands would correctly constrain the inputs as per the requirements in the attached figure..

https://alteraforum.com/forum/attachment.php?attachmentid=13431&stc=1

what the diagram shows : I have an 8-bit port on a Video Decoder which outputs data to the FPGA.The clock used in the FPGA is output from the

same device.The device is configured to change its data on the falling edge of the clock.The device opertes on a 27 Mhz clock i.e a period of 37.037 ns.The datasheet lists T5 as Output Hold Time and gives a minimum Value of 10ns.The datasheet lists T6 as Output Delay Time and gives a maximum Value of 25ns.So, I conclude that with respect to the falling edge of the clock, the data begins to change 10ns the after falling edge and regains stability 15ns later.Is this what the diagram depicts?If so, I think the constrains that specify this should be :

create_clock -period 37.037 -name clkvin;# virtual clock for input constraintset_input_delay -clock clkvin -max 25  -clock_fallset_input_delay -clock clkvin -min 10  -clock_fall

Setting the input delay constraints like this ends up giving the following failing constraints in the Timing Analyzer.

https://alteraforum.com/forum/attachment.php?attachmentid=13432&stc=1

CH2-BITEC-IN are the physical input pins on the HSMC connector.The data on these pins is registered with the clock CH2-BITEC-CLK like so :

always @ (posedge CH2_BITEC_CLK) begin input_data <= CH2_BITEC_IN; end

Have I deduced the requirements correctly from the diagram? If so, then why does the design fail and how can I make it work?

Thank you!