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Altera_Forum
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9 years ago

set_input_delay And set_output_delay .SDC Constraints

Hello! I have little familiarity with the set_input_delay and set_output_delay SDC and was wondering whether the following commands would correctly constrain the inputs as per the requirements in th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

you need to set offsets as they are:

min = 15 &max = 16 and both from falling edge. It should be no problem to pass

How did get those figures of 25/10??

I needed glasses.min = t5 &max = t6 yes. If it fails then you need to try PLL or use same edge. Also you have assumed board delays to be equal for clk/data