set_input_delay And set_output_delay .SDC Constraints

On a side note, Here's what I think setting the output_delay -max attribute does : It informs the synthesizer that the input register, the one with its "D" pins connected directly to the input pins on the FPGA can not be sampled at the positive edge of the same clock that is used between two internal registers on the FPGA. Consequently, when I constrain the output_delay -max to be 25 ns, it leaves out 12 ns (in a 37ns) for the input pins data to appear at the output of the register and then be used for any combinational logic(like comparators e.t.c) before the final result.When the constraints fail, this simply means that the remaining time isn't sufficient for the subsequent processing? If so, then