set_input_delay And set_output_delay .SDC Constraints

Thank you for the prompt feedback and I apologize for the poor quality of the picture and any other shortcomings!

Just to be certain, I wrote 't5' and 't6' on the left side of the diagram and not 15 and 16.Again, My bad.Now, as per the diagram attached the data sheet lists the values for 't5' and 't6' labelled in the diagram as "10ns" and "25ns" . My reasoning behind arriving at these values was that 10ns after the falling clock edge, the data begins to change and 15 ns later (25 ns after falling edge),new data is available, hence the min and max values, Please correct me if I'm wrong,

Secondly, when I remove the -clock fall constraint, the analyzer reports no warnings.Why is this so?

If it should still be 15 and 16 then, I am hopelessly lost. :( . Please have a look at the attached diagrams.

https://alteraforum.com/forum/attachment.php?attachmentid=13434&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=13435&stc=1