Honored ContributorI am using a FPGA which has four PLLs. In my design I use the altpll megafunction to get a PLL. Quartus assings this PLL to the PLL4-location, but I need it to be on the PLL1-location because I want to use the dedicated output pin of PLL1. How can I force Quartus to use PLL1 instead of PLL4?
Honored ContributorI believe there are ways to assign PLL locations, and I'm sure you can assign the altclkctrl to a location(which forces the PLL location), but the simplest way is to assign the clock input to use that dedicated input. (Although I would assume that would have been assigned before the PLL output is assigned, so that may be the problem, i.e. it's assigned to a location that drives another PLL...?) Is this a source-synchronous output? If so, I definitely wouldn't use the dedicated PLL output. In general, I'm not a big fan of that output because it's limited in what it can do, and I've seen people get by using regular I/O as clock outputs all the time. If you need really low jitter or great duty cycle or something like that, it may be better, but I haven't seen any cases where someone said, I wish we had put that on the dedicated PLL clock output. (Although I'd love to hear more comments...)
Honored ContributorThe first question is, if you are using a FPGA family that allows clocking of PLLs from global clock networks, e.g. Cyclone 3? Other wise, it simply don't work. Did you try, to assign the output to the PLL? In many cases, Quartus performs the assignment automaticly, if ever possible. If Quartus doesn't for some reason, but the assignment is supported by the FPGA hardware, you can assign the PLL location in assignment editor.
Regarding Rysc's comment, I'm using dedicated PLL outputs where applicable. The only advantage is, that they have less routing delay and skew. So you get an early clock, that's often required to drive external registers without particular fitter effort. Jitter of PLL outputs isn't really low anyway, and don't get considerably worse when using regular IO, I think.Honored ContributorThanks to both of you for your comments!
I have to admit that I'm not that experienced when it comes to Quartus. But I found a solution for my problem. I simply put the lineset_location_assignment PLL_1 -to "altpll0:inst1"
