select PLL in FPGA-Design

I believe there are ways to assign PLL locations, and I'm sure you can assign the altclkctrl to a location(which forces the PLL location), but the simplest way is to assign the clock input to use that dedicated input. (Although I would assume that would have been assigned before the PLL output is assigned, so that may be the problem, i.e. it's assigned to a location that drives another PLL...?) Is this a source-synchronous output? If so, I definitely wouldn't use the dedicated PLL output. In general, I'm not a big fan of that output because it's limited in what it can do, and I've seen people get by using regular I/O as clock outputs all the time. If you need really low jitter or great duty cycle or something like that, it may be better, but I haven't seen any cases where someone said, I wish we had put that on the dedicated PLL clock output. (Although I'd love to hear more comments...)