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Altera_Forum
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16 years ago

select PLL in FPGA-Design

I am using a FPGA which has four PLLs. In my design I use the altpll megafunction to get a PLL. Quartus assings this PLL to the PLL4-location, but I need it to be on the PLL1-location because I want ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks to both of you for your comments!

I have to admit that I'm not that experienced when it comes to Quartus. But I found a solution for my problem. I simply put the line 

set_location_assignment PLL_1 -to "altpll0:inst1"
into my .qsf file.

I'm not sure if I really need the dedicated output. But using it has at least one advantage: Quartus will not say that I should use dedicated outputs...